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| STD22NM20N N-CHANNEL 200V - 0.088 - 22A DPAK ULTRA LOW GATE CHARGE MDmeshTM II MOSFET Table 1: General Features TYPE STD22NM20N Figure 1: Package RDS(on) < 0.105 ID 22 A VDSS 200 V WORLDWIDE LOWEST GATE CHARGE TYPICAL RDS(on) = 0.088 HIGH dv/dt and AVALANCHE CAPABILITIES LOW INPUT CAPACITANCE LOW GATE RESISTANCE 3 1 DESCRIPTION This 200V MOSFET with a new advanced layout brings all unique advantages of MDmesh technology to lower voltages. The device exhibits worldwide lowest gate charge for any given onresistance. Its use is therefore ideal as primary switch in isolated DC-DC converters for Telecom and Computer applications. Used in combination with secondary-side low-voltage STripFETTM products, it contributes to reducting losses and boosting effeciency. DPAK Figure 2: Internal Schematic Diagram APPLICATIONS The MDmeshTM family is very suitable for increasing power density allowing system miniaturization and higher efficiencies Table 2: Order Codes SALES TYPE STD22NM20NT4 MARKING D22NM20N PACKAGE DPAK PACKAGING TAPE & REEL Rev. 5 November 2005 1/10 STD22NM20N Table 3: Absolute Maximum ratings Symbol VDS VDGR VGS ID IDM (*) PTOT dv/dt (2) Tj Tstg Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25 Drain Current (continuous) at TC = 100 Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Peak Diode Recovery voltage slope Storage Temperature Max Operating Junction Temperature Value 200 200 20 22 13.7 88 100 0.8 14 150 -65 to 150 Unit V V V A A A W W/C V/ns C C (*) ISD 22A, di/dt 400A/s, VDD = 80% V(BR)DSS Table 4: Thermal Data Rthj-case Rthj-amb Rthj-ambTl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Junction-pcb (*) Maximum Lead Temperature For Soldering Purpose 1.25 100 43 275 C/W C/W C/W C (*) When mounted on 1 inch FR-4 board, 2 oz Cu, t 10 sec Table 5: Avalanche Characteristics Symbol IAS EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = 22 A, VDD = 50 V) Max Value 22 380 Unit A mJ 2/10 STD22NM20N ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) Table 6: On/Off Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 1mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20V VDS = VGS, ID = 250 A VGS = 10V, ID = 11 A 3.5 4.2 0.088 Min. 200 1 10 100 5 0.105 Typ. Max. Unit V A A nA V Table 7: Dynamic Symbol gfs (2) Ciss Coss Crss Coss eq. (**) RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitiance Gate Input Resistance Test Conditions VDS = 15 V, ID=11 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 8 800 330 130 225 5 Max. Unit S pF pF pF pF VGS = 0 V, VDS = 0 V to 400 V f= 1MHz Gate DC Bias = 0 Test Sgnal Level = 20 mV Open Drain VDD = 100 V, ID = 11 A RG = 4.7 VGS = 10 V (see Figure 15) VDD = 100 V, ID = 20 A, VGS = 10 V (see Figure 19) td(on) tr tr(Voff) tf Qg Qgs Qgd Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge 40 15 40 11 32 6 25 50 ns ns ns ns nC nC nC (**) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 8: Source Drain Diode Symbol ISD ISDM (1) VSD (2) trr Qrr IRRM trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 20 A, VGS = 0 ISD = 20 A, di/dt = 100 A/s VDD = 100V, Tj = 25C (see test circuit, Figure 17) ISD = 20 A, di/dt = 100 A/s VDD = 100V, Tj = 150C (see test circuit, Figure 17) 160 960 12.8 225 1642 15 Test Conditions Min. Typ. Max. 22 88 1.3 Unit A A V ns C A ns C A (1) Pulse width limited by safe operating area. (2) Pulsed: Pulse duration = 300 s, duty cycle 1.5 % 3/10 STD22NM20N Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/10 STD22NM20N Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature Figure 11: Source-Drain Diode Forward Characteristics Figure 14: Normalized BVdss vs Temperature 5/10 STD22NM20N Figure 15: Unclamped Inductive Load Test Circuit Figure 18: Unclamped Inductive Wafeform Figure 16: Switching Times Test Circuit For Resistive Load Figure 19: Gate Charge Test Circuit Figure 17: Test Circuit For Inductive Load Switching and Diode Recovery Times 6/10 STD22NM20N TO-252 (DPAK) MECHANICAL DATA mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 V2 0.60 0 o DIM. 2.20 0.90 0.03 0.64 5.20 0.45 0.48 6.00 6.40 4.40 9.35 inch MAX. 2.40 1.10 0.23 0.90 5.40 0.60 0.60 6.20 6.60 4.60 10.10 MIN. 0.087 0.035 0.001 0.025 0.204 0.018 0.019 0.236 0.252 0.173 0.368 0.031 1.00 8 o TYP. TYP. MAX. 0.094 0.043 0.009 0.035 0.213 0.024 0.024 0.244 0.260 0.181 0.398 0.8 0.024 0 o 0.039 0o P032P_B 7/10 STD22NM20N DPAK FOOTPRINT All dimensions are in millimeters TAPE AND REEL SHIPMENT REEL MECHANICAL DATA DIM. A B C D G N T 1.5 12.8 20.2 16.4 50 22.4 18.4 13.2 mm MIN. MAX. 330 0.059 0.504 0.520 0.795 0.645 0.724 1.968 0.881 BULK QTY 2500 inch MIN. MAX. 12.992 TAPE MECHANICAL DATA DIM. A0 B0 B1 D D1 E F K0 P0 P1 P2 R W BASE QTY 2500 mm MIN. 6.8 10.4 1.5 1.5 1.65 7.4 2.55 3.9 7.9 1.9 40 15.7 16.3 inch MIN. MAX. 7 0.267 0.275 0.409 0.417 0.476 0.059 0.063 0.059 0.065 0.073 0.291 0.299 0.100 0.108 0.153 0.161 0.311 0.319 0.075 0.082 1.574 0.618 0.641 MAX. 10.6 12.1 1.6 1.85 7.6 2.75 4.1 8.1 2.1 8/10 STD22NM20N Table 9: Revision History Date 31-May-2004 15-Mar-2005 09-May-2005 09-Jun-2005 04-Nov-2005 Revision 1 2 3 4 5 Description of Changes First Release. Update version. Complete version. New update Corrected value on Table 8 9/10 STD22NM20N Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 10/10 |
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